1. Field
This present invention is a structure for addressing power integrity issues associated with automating testing of very high speed integrates circuit devices in a singulated or unsingulated die (wafer) form. In particular the present invention provides a structure for an improved pitch translation substrate and for locating or embedding passive components closer to the pitch translation substrate.
2. Definitions
Certain terminology is defined below for a better understanding of the disclosure of the present invention.
Probe card: A multilayer printed circuit board, usually 3 mm to 8 mm thick. It is used as the electrical signal routing interface from the (automated) test system to the pitch translation substrate. The probe card itself translates pitch but on a much larger scale. The probe card also provides mechanical support to the pitch translation substrate and the probe housing. The probe card is described and shown in drawings for clarity.
Pitch Translation Substrate: The pitch translation substrate (PTS) provides an interface between the probe card and the probe housing assembly. Standard printed circuit board material does not allow pitches fine enough to support the electrical connect patterns on an integrated circuit die. The PTS uses special materials and is much smaller than the probe card, allowing the electrical signal routing to exist between the die and the probe card. Most PTS devices are commonly known by the material used to manufacture them.
These include, but are not limited to, “MLC” (multi-layer ceramic), “MLO” (multilayer organic), “Si Sub” (silicon substrate), “Glass sub” (glass substrate). The main focus of this disclosure is the PTS, as improved power integrity requires changes to this structure.
Probe Housing Assembly: The probe housing assembly includes the actual electrical probes between the integrate circuit die and the PTS. The probe housing is described and shown in drawings for clarity.
Die: The die references the actual electrical integrated circuit for which the entire probe assembly is designed to test. Typically die are manufactured in bulk on a silicon wafer; this document refers to this form as the “unsingulated” form. Unsingulated form is the most common form for die testing. Die may be tested individually in “singulated” form, where each die is physically separated from the wafer. Die may also be tested in a “reconstituted” wafer form, where by the die is placed at a different spacing than on the original wafer. The probe assembly, including the probe card, pitch translation substrate, and probe housing, is used in any one of these three forms for die test. The main purpose of addressing power integrity/impedance issues in this disclosure is to allow the die to be tested as close as possible to its mission mode (end user application) prior to packaging.
Wafer: The wafer—typically 200 mm, 300 mm, or 450 mm in diameter—is the base upon which each individual die is manufactured. One wafer may contain 30-40 to several 1000 individual die in their unsingulated form. The wafer is in diagrams for clarity. When shown, the reader should assume the test probes connect to an individual die on the wafer.
Chuck: The chuck is a large platen, usually made of metal, that supports and clamps the wafer/die during test. The chuck also is the moving mechanism, which increments from die to die so that each die may be tested. The chuck is shown in drawings for clarity.
Power Integrity: A description of how well the probe assembly can meet transient current demands placed on supply and ground pins when a device operates. A critical FIG. of merit for power integrity is “supply loop impedance” over frequency.
Supply Loop Impedance: This is a measure of how much voltage will drop across the supply and ground pins (power pins) of the probe assembly when the integrated circuit under test (die) places a sinusoidal or transient current demand on the power pins (Voltage Drop/Current in the frequency domain, F). The lower the supply loop impedance, the less the voltage drops. Loop impedance indicates that both the supply and ground pins have been included. In over-simplified terms, loop impedance is often described in the industry as “self inductance”, where self inductance (LS) is equal to 3/2 of the loop inductance (LL) and |j2πF LL| is equal to the loop impedance associated with a simple inductance. “Loop impedance” is the more correct and general term as it accounts for non-ideal inductor occurrences in the supply-ground path such as resonance points.
Data Eye: Because supply loop impedance may not directly translate into improvements in performance, a data eye is also used as a visual FIG. of merit. The data eye overlays digital data in a data stream from the die under test using periodic time division, usually associated with an operating clock or embedded clock. An open center data eye indicates good operational margins, where as errors may occur as the eye center closes.
Compliant Electrical Interconnect: An electrical interconnect device that requires some level of compression to make electrical contact between desired pads on two different surfaces.
Compliant interconnects allow for higher levels of coplanar discrepancies between two surfaces, movement (i.e. thermal expansion relief) and usually, ease of interchangeability. Examples include, but are not limited to, spring contact probes, conductive elastomer sheets, and conductive elastomer pins.
Permanent Electrical Interconnect: An electrical interconnect device that makes a permanent bond and electrical contact between desired pads on two different surfaces. Permanent interconnects are characterized by lower contact resistance, high structural rigidity, and a far greater application of heat and force to de-bond the two surfaces. Examples include, but are not limited to solder and thermal-sonically bonded copper pillars.
Redistributed Layer (RDL): An electrical routing layer that exists within the pitch translation substrate and serves the purpose of point to point connections from the very fine pitch of the die to the much large pitch of the probe card. In many cases there may be intermediate steps and multiple interconnecting redistribution layers.
3. The Related Art
FIG. 11 illustrates a sectional view of the related prior art and is provided for reference purposes only. In the prior art, a wafer probe or die probe setup involves the probe card [80], the attach mechanism [82] pitch translation substrate [81], the probes and probe head [83], and the wafer prober chuck (simply chuck) [85]. In operation, the chuck [85] moves from die to die in an X-Y direction. When the next die to test has been reached the chuck [85] raises the wafer/die [84] into the probe head [83]. The probes [83] make mechanical contact to the die on the wafer [84] and thus provide a conductive electrical path, allowing the die [84] to be tested.
In the prior art passive electrical components [86] (generally capacitors) provide charge storage for transient current demands (charge/time) from the die [84] during its operation and while under electrical test. A common practice in the prior art uses the area directly above the die [84] on the pitch translation substrate [81] and the probe card [80] for routing.
The physical distance between the passive electrical components [86] and the die under test on the wafer [84] directly impacts how well the stored charged in the passive electrical components [86] can be delivered to meet the transient current demands of the die [84]. If the distance is longer, there will be more delay that will occur as a result of the length of the distance. Since a decoupling capacitor acts as RF short, this delay generally has an inductive effect up to ˜1 Ghz, and then vacillates between higher impedance and a lower impedance as frequency increases (See FIG. 12B). This is a common distributed impedance affect. Due to the thickness of the probe card varying from application to application, the exact locations of the resonant points change. The net impact is shown in FIGS. 13B, 14B, 15B, and 16B. Based on the data eyes shown in FIGS. 13B and 14B, the die stops working properly between 667 MB/s and 1000 MB/s. FIG. 16B shows a 1 GHz clock. In this case ringing tends to align, but the edge transitions heavily distorted.
In somewhat over-simplified terms, the issue may be explained by simplifying the effective loop impedance to a loop inductance LL. Voltage Drop is equal to the loop inductance multiplied by the derivative of the transient current demand relative to time. ΔV=LL X dI/dt. When transistor on the die transition state a transient current is created and relates, in simplified terms, to the amount of parasitic capacitance Cp and partially on/partially-off current the transistors must drive. As LL increases, the output response of the transistors has delayed, dampened sinusoidal ringing or a delayed reduced edge. In this simplified case, both possible responses relate to the dominant second order response of LL and Cp—often modeled as a second order differential equation. The ringing is most noticeable in FIG. 14B.
4.
Standard prior art technology uses a solder reflow process to attach passive components to the probe card. This attach method has the benefit of 30+ years of industry knowledge and implementation. Therefore it is low-cost and reliable—both come at the expense of performance. It would be desirable to provide a structure or structures that overcomes the aforementioned problems associated with the aforementioned prior art proposals.